© 2017 IEEE.Ī 16 bit low power pipelined RISC processor is proposed by us in this paper, the RISC processor consists of the block mainly ALU, Universal shift register and Barrel Shifter. We evaluate the performance of system using several different test sets and observe that, DTW models presented the good results in all cases. 1i by Xilinx Synthesis Technology and the target device used was XC 4085 XLA-07-hq304 FPGA.
![modelsim 10.3c modelsim 10.3c](https://i.ytimg.com/vi/fQKTbyQHAjE/maxresdefault.jpg)
The work was carried out on Xilinx ISE 14. The complete coding for each and every module was done in VHDL. We have implemented our project on FPGA which takes its place in the continuing evolution of VLSI circuit technology towards the denser and faster circuits. Adopting DTW algorithm, we can produce a chip having word spotting function at a low cost. Dynamic Time Warping algorithm effectively cures such problems. Due to this fact, speech recognition results in error or rejection. When one speaks the same word, the time-length of the word changes in each time. This obvious point not only underlies the difficulty in speech recognition but also means that we able to extract more than just a sequence of words from the signal. No two utterances of the same word or sentence are likely to give rise to the same digital signal. The input signal must be matched against a stored pattern and then makes a decision of accepting or rejecting a match. This involves preprocessing the acoustic signals to parameterize it in a more usable and useful form. Speech recognition is the process of finding a linguistic interpretation of a spoken utterance typically, this means finding the sequence of words that were spoken.
#Modelsim 10.3c software#
The first speech recognition software for computers was PLAINTALK by Apple Computers for Macinosh. However, the first commercial voice recognition or speech recognition device dates back to 1978 when Texas Instruments introduced the first speech synthesizer in the form of children's toy. Electronics speech synthesis was developed in 1936 by AT & T, Bell's lab as a research tool. Speech recognition is a technology where the computer understands the word given through speech, rather than using a keyboard. In this paper, we present a new approach of implementing DTW algorithm on FPGA for to voice recognition.
![modelsim 10.3c modelsim 10.3c](https://www.researchgate.net/profile/Gupta-Ashutosh/publication/228309783/figure/fig4/AS:652217749102594@1532512237325/Simulated-Waveform-of-Transmitter.png)
The power has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.3.
![modelsim 10.3c modelsim 10.3c](https://www.researchgate.net/profile/Gupta-Ashutosh/publication/41055080/figure/fig2/AS:650831812624394@1532181804731/Simulation-result-for-controller-state-machine.png)
![modelsim 10.3c modelsim 10.3c](https://de.mathworks.com/help/examples/hdlverifier/win64/xxsvdpi_FIFO_Interface9.png)
93% and 95.53% reduction in total clock power, 89.73%, 91.35% and 92.85% reduction in I/Os power, 67.14%, 62.84% and 74.34% reduction in dynamic power and 25.47%, 29.05% and 46.13% reduction in total supply power at 20 MHz, 200 MHz and 2 GHz frequency respectively. The design is verified using System Verilog on QuestaSim in UVM environment. The circuit has been simulated on Modelsim 10.3c. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. This gated clock is used to control the multiplexer based 64-bit ALU. We have used negative latch based circuit for generating gated clock. We have designed a 64-bit ALU with a gated clock.
#Modelsim 10.3c full#
The 64-bit ALU is designed using multiplexer based full adder cell. 64-bit energy efficient Arithmetic and Logic Unit using negative latch based clock gating technique is designed in this paper.